The invention relates to a semiconductor memory device including an improved substrate structure and a method of fabricating the same.
The semiconductor memory device including a memory cell array area and a peripheral circuit area is formed on a surface of a semiconductor substrate such as silicon substrate. High integration and excellent device performance, especially excellent transistor characteristics are most important to such memory cell devices. The realization of the high integration and excellent device performance such as excellent transistor characteristics will now be considered.
The accomplishment of the high integration of the memory device depends upon a photo-lithography technology for delineating fine patterns. The implementation of the fine pattern, and thus the fine etching pattern further depends upon not only a resolution of photo resist patterns but the irregularity possessed by a surface of the memory device.
The excellent transistor characteristics depends upon the impurity concentration of the surface region in the semiconductor substrate.
For consideration of the above matters, dynamic random access memory cells (DRAM cells) involving stacked capacitor cells will be taken up as a typical semiconductor memory device. FIG. 1 illustrates a conventional structure of the DRAM cells comprising the peripheral circuit area and the memory cell array area involving the stacked capacitors. The structure of the conventional DRAM cells has a p-type silicon substrate 1. The p-type silicon substrate 1 having a flat surface comprises a memory cell array area 110 and a peripheral circuit area 113.
A p.sup.+ -type well region which is not illustrated is formed in the memory cell array area 110 of the p-type silicon substrate 1. Gate oxide films 11 are formed in the surface of the memory cell array area 110 and the peripheral circuit area 113 of the p-type silicon substrate 1. A field oxide film 10 is formed in the surface of the p-type silicon substrate 1 so as to separate the memory cell array area 110 from the peripheral circuit area 113. Both the field oxide film 10 and the gate oxide film 11 are formed by using a selective oxidation such as local oxidation of silicon (LOCOS). Gate electrodes 12 are formed on the gate oxide film 11 in both the memory cell array area 110 and the peripheral circuit area 113. An ion-implantation of an opposite conductive type impurity to that of the silicon substrate 1, or the donor is carried out by using the self-alignment technique so that source and drain diffusion regions 111 and 112 are formed in the memory cell array area 110 and the peripheral circuit area 113, thereby resulting in a self-aligned gate structure. The result is that field effect transistors are formed in both the memory cell array area 110 and the peripheral circuit area 113. A silicon oxide film 14 is formed by using a chemical vapor deposition so as to cover an entire surface of the device, and thus to cover the gate electrodes 12. The silicon oxide film 14 serves as an inter-layer insulator. A bottom electrode 15 of a stacked capacitor is formed in the memory cell array area 110 so as to be electrically connected to the source region 112 of the transistor. A capacitive insulation film is so formed as to cover the bottom electrode 15 of the stacked capacitor. A top electrode 17 of the stacked capacitor is formed on the capacitive insulation film 16 and on the silicon oxide film 14 serving as the inter-layer insulator, thereby resulting in a formation of a stacked capacitor. A silicate glass film such as a boro-phospho-silicate glass film 18 is so formed as to cover an entire surface of the device, followed by a heat treatment thereby resulting in a reflow of the boro-phospho-silicate glass film 18. With respect to the reflow of the boro-phospho-silicate glass film 18, the planarization of the boro-phospho-silicate glass film 18 in the memory cell array area 110 is likely to be strongly promoted rather than that in the peripheral area 113, because the memory call area 110 has a dense pattern rather than the thin pattern of the peripheral circuit area 113.
Although the reflow of the boro-phospho-silicate glass film 18 caused by the heat treatment contributes the planarization or leveling of the surface of the device, but it is insufficient. Thus, the surface of the memory device has an irregularity. For example, the surface of the boro-phospho-silicate glass film 18 in the memory cell array area 110 exists at a higher level than that in the peripheral circuit area 113. The difference in heights of the surfaces of the memory cell array area and the peripheral circuit area 113 is mainly caused by the existence of the stacked capacitors 15, 16 and 17. The difference in heights of the both surfaces of the memory cell array area 110 and the peripheral circuit area 113 corresponds approximately to the height of the stacked capacitor 15, 16 and 17.
The difference in levels of surfaces of both the memory cell array area 110 and the peripheral circuit area 113 makes it difficult to accomplish the fine pattern by the photo-lithography. Thus, such irregularity in levels of the surface of the memory device causes a difference in depths of focus of the photo-lithography. This makes it difficult to implement the fine pattern and thus to promote the high integration.
Therefore, the realization of the high integration of the memory cell device requires the fine pattern of the photo-lithography. The implementation of the fine pattern requires the difference in levels of the surface of the device to be reduced, and thus the planarization of the surface of the device to be promoted.
To comply with the above requirements, the prior art employs a substrate including a recess portion on its surface at the memory cell array area 110. This technique is disclosed in 1988 VLSI symposium pp. 17-18, "A HALF MICRON TECHNOLOGY FOR AN EXPERIMENTAL 16 MBIT DRAM USING i-LINE STEPPER", Y. Kawamoto at al. Such technique for reduction of the difference in surface levels between the memory cell array area and the peripheral circuit area will subsequently be described with reference to FIG. 2.
A silicon substrate 1 including a memory cell array area 900 and a peripheral circuit area 901 is prepared, after which a surface of the silicon substrate 1 is subjected to a selective oxidation so that a silicon oxide film is formed in the surface of the silicon substrate 1, but only in the memory cell array area 900. Subsequently, the silicon oxide film is removed thereby resulting in a formation of a recessed portion in the surface in the memory cell array area 900. The existence of the recessed portion in the memory cell array area 900 of the silicon substrate 1 will be permissive of reducing the difference in surface levels of the memory cell array area 900 and the peripheral circuit area 901.
For understanding concretely the above advantages, the structure of the conventional DRAM cells formed on the p-type silicon substrate 1 including the recessed portion is described with reference to FIG. 3. The p-type silicon substrate 1 includes a recessed portion in the memory cell array area 110. Thus, the level of the surface in the memory cell array area 110 of the silicon substrate 1 is lower than that in the peripheral circuit area 113. The structure of the device illustrated in FIG. 3 is analogues to that of FIG. 1, except that the recess portion is formed in the surface of the substrate in the memory cell array area.
A p.sup.+ -type well region which is not illustrated is formed in the memory cell array area 110 of the p-type silicon substrate 1. Gate oxide films 11 are formed in the surfaces of the memory cell array area 110 and the peripheral circuit area 113 of the p-type silicon substrate 1. A field oxide film 10 is formed in the surface of the p-type silicon substrate 1 so as to separate the memory cell array area 110 from the peripheral circuit area 113. As the field oxide film 10 exists across the bounds between the memory cell array area 110 and the peripheral circuit area 113, the field oxide film 10 has a difference in level. Thus, a part of the field oxide film 10 overlays the surface of the substrate 1 in the memory cell array area 110 including the recessed portion. Both the field oxide film 10 and the gate oxide film 11 are formed by using a selective oxidation such as local oxidation of silicon (LOCOS). Gate electrodes 12 are formed on the gate oxide films 11 in the both memory cell array area 110 and peripheral circuit area 113. An ion-implantation of an impurity of opposite conductive type to the silicon substrate 1, or the donor is carried out by using the self-alignment technique so that source and drain diffusion regions 111 and 112 are formed in the memory cell array area 110 and in the peripheral circuit area 113, thereby resulting in a self-aligned gate structure. The result is that field effect transistors are formed in both the memory cell array area 110 and in the peripheral circuit area 113. The transistor involved in the memory cell array area 110 exists at a lower level than that in the peripheral circuit area 113 by a difference approximately in levels of the surfaces of the silicon substrate 1. A silicon oxide film 14 is formed by using a chemical vapor deposition so as to cover an entire surface of the device, and thus to cover the gate electrodes 12. The silicon oxide film 14 will serve as an interlayer insulator. A bottom electrode 15 of a stacked capacitor is formed in the memory cell array area 110 so as to be electrically connected to the source region 112 of the transistor. A capacitive insulation film 16 is so formed as to cover the bottom electrode 15 of the stacked capacitor. A top electrode 17 of the stacked capacitor is formed on the capacitive insulation film 16 and the silicon oxide film 14 serving as the interlayer insulator, thereby resulting in a formation of a stacked capacitor in the memory cell array area 110. A silicate glass film such as a boro-phospho-silicate glass film 18 is so formed as to cover an entire surface of the device, followed by a heat treatment thereby resulting in a reflow of the boro-phospho-silicate glass film 18. With respect to the reflow of the boro-phospho-silicate glass film 18, the planarization of the boro-phospho-silicate glass film 18 in the memory cell array area 110 is strongly promoted rather than that in the peripheral circuit area 113, because the memory call array area 110 has a dense pattern rather than the thin pattern of the peripheral circuit area 113.
Although the reflow of the boro-phospho-silicate glass film 18 caused by the heat treatment contributes the planarization, or leveling of-the surface of the device, but it is insufficient. Since the silicon substrate 1 includes the recessed portion in the memory cell array area 110, the difference in levels of surfaces of the memory cell array area 110 and the peripheral circuit area 113 is, however, reduced by the depth of the recessed portion in the silicon substrate 1. Thus, the surface of the memory device has a reduced irregularity. The surface of the boro-phospho-silicate glass film 18 in the memory cell array area 110 is higher than that in the peripheral circuit area 113, but it is unremarkable. Thus, the recessed portion in the silicon substrate 1 enables the difference in levels of the surfaces of memory cell device to be substantially reduced so as to be unremarkable for the photo-lithography technique.
The unremarkable difference in levels of both the memory cell array area 110 and the peripheral circuit area 113 is free from the difficulty in accomplishment of the fine pattern by the photo-lithography. Thus, such unremarkable irregularity in levels of the surface of the memory device makes a difference in depths of focus of the photo-lithography unremarkable. This makes it possible to implement the fine pattern and thus to promote the high integration. Therefore, the silicon substrate 1 including the recessed portion promotes the realization of the high integration of the memory device provided by the fine pattern of the photo-lithography.
Although the formation of the recessed portion in the silicon substrate 1 contributes the realization of the high integration of the memory device, another problem with the transistor characteristics is still outstanding. Then, the transistors in the memory cell array area 110 and the peripheral circuit area 113 are respectively required to have different performances, and thus properties from each other. The transistor characteristics, and thus performances depend upon the impurity concentrations in the silicon substrate 1, but at the surface region thereof, because a part of the surface region of the silicon substrate 1 serves as a channel region of the field effect transistor. The impurity concentration of the surface region of the silicon substrate 1 is required to be different between the memory cell array area 110 and the peripheral circuit area 113. It is desirable that the impurity concentrations in the memory cell array area 110 and in the peripheral circuit area 113 are respectively so determined that each of the transistors in the memory cell array area 110 and the peripheral circuit area 113 exhibits best performances and excellent properties. For example, the surface of the silicon substrate 1 in the memory cell array area 110 is required to have a higher impurity concentration than that in the peripheral area 113. The impurity concentration of the surface in the conventional silicon substrate 1 has, however, an uniformity. Then, the conventional silicon substrate 1 having the uniform impurity concentration at the surface is impossible of bringing out the best performance of each of the transistors in the memory cell array area 110 and in the peripheral circuit area 113. Therefore, it is desirable that the silicon substrate 1 includes surface areas in the memory cell array area 110 and the peripheral circuit area 113 having suitable impurity concentrations different from each other. Needless to say, it is also desirable that the silicon substrate has a recessed portion at the memory cell array area 110, which makes the reduction of the difference in levels of the surface between the memory cell array area 110 and the peripheral circuit area 113. The realization of not only the higher integration but the excellent device performance requires the development of a novel silicon substrate and a novel method of fabricating the same.